The present invention relates to semiconductor integrated circuits suitable for high-speed and low-power operation, and particularly to a semiconductor integrated circuit formed of small-geometry MOS transistors.
The semiconductor integrated circuits have so far been developed toward the scaling down of MOS transistors. However, since the minute structure of MOS transistors reduces their breakdown voltage the more as the degree of the minuteness becomes greater, the operating voltage of the small-geometry MOS transistors must be lowered, as described in International Symposium on VLSI Technology, Systems and Applications, Proceedings of Technical Papers, pp.188-192(May 1989). The operating voltages of the semiconductors used in the battery-operated portable electronic apparatus must be further reduced for their low power consumption.
In order to maintain their high-speed operation under reduced operating voltages, it is also necessary to decrease the threshold voltage (VT) of the MOS transistors. The reason for this is that the operating speed is governed by the effective gate voltage of the MOS transistors, or the remainder of the subtraction of VT from the operating voltage, or that it increased with the increase of this effective gate voltage. For example, in a 16-gigabit DRAM which is expected to have 0.15 xcexcm or below in effective channel length, about 4 nm in gate oxide film thickness, 1 V in standard operating voltage within chip and about 1.75 V in boosted word line voltage, the constant current threshold voltage of transistors is calculated to be xe2x88x920.04 V. The term, constant current threshold voltage of transistors is the gate-source voltage under the conditions of a ratio, 30 of effective channel width to effective channel length and a drain current of 10 nA. In this case, the substrate-source voltage is 0, the junction temperature is 25xc2x0 and a typical condition is assumed. For simplicity, the threshold voltage of p-channel MOS transistors is shown with the opposite sign.
When VT is reduced, however, the drain current cannot be completely cut off due to the drain current characteristic of the subthreshold region of MOS transistors. This problem will be described with reference to FIG 22A which shows a conventional CMOS inverter. When the input signal IN to the CMOS inverter has a low level (=Vss), the n-channel MOS transistor MN is turned off. When the input signal IN has a high level (=Vcc), the p-channel MOS transistor Mp is turned off. Therefore, in either case, from the ideal point of view, no current flows from the high source voltage Vcc through the CMOS inverter to the low source voltage Vss, or ground potential.
When the threshold voltage VT of the MOS transistors is reduced, however, the subthreshold characteristic cannot be neglected. As shown in FIG. 22B, the drain current IDS in the subthreshold region is proportional to the exponential function of the gate-source voltage VGS, and expressed by the following equation (1).                               I                      D            ⁢                          xe2x80x83                        ⁢            S                          =                              I            0                    ·                      W                          W              0                                ·                      10                                                            V                                      G                    ⁢                                          xe2x80x83                                        ⁢                    S                                                  -                                  V                  T                                            S                                                          (        1        )            
where W is the channel width of the MOS transistors, I0 and W0 are the current value and channel width used when VT is defined, and S is the subthreshold swing (the reciprocal of the gradient of the VGS-log IDS characteristic). Thus, the drain current in the subthreshold region (, or the subthreshold current) flows even under VGS=0. The subthreshold current can be expressed by the following equation (2).                               I          L                =                              I            0                    ·                      W                          W              0                                ·                      10                          -                                                V                  T                                S                                                                        (        2        )            
When the input signal to the CMOS inverter shown in FIG. 22A is not changed, or when it is not operated, the off-state-transistor of the CMOS inverter is at VGS=0. Therefore, the current flowing from the high source voltage Vcc, through the CMOS inverter to the low source voltage Vss, or ground potential is the current IL which flows in the off-state transistor of the CMOS inverter.
This subthreshold current, as shown in FIG. 22B, is exponentially increased from IL to ILxe2x80x2 when the threshold voltage is decreased from VT to VTxe2x80x2.
Although the increase of VT or the reduction of S reduce the subthreshold current as will be seen from the equation (2), the increase of VT, incurs the reduction of the speed due to the decrease of the effective gate voltage, while the reduction of S will be difficult for the following reason.
The subthreshold swing S can be expressed by using the capacitance COX of the gate dielectric and the capacitance CD of the depletion region under the gate as in the following equation (3).                     S        =                                                                              k                  ·                  T                  ·                                      l                    n                                                  ⁢                10                            q                        ⁢            1                    +                                    C              D                                      C                              O                ⁢                                  xe2x80x83                                ⁢                X                                                                        (        3        )            
where k is the Boltzmann constant, T is the absolute temperature and q is the elementary charge. As will be seen from the equation (3), the condition of Sxe2x89xa7kT ln 10/q is limited for any values of COX and CD. Thus, it is difficult for S to be reduced to 60 mV or below at room temperature (about 300 k).
Thus, in the semiconductor integrated circuit including MOS transistors with a low value of VT the amount of DC current consumption of non-operating circuits is remarkably increased because of the phenomenon mentioned above when the operating voltage becomes low (for example, 2 V or 2.5 V). Particularly, upon high-temperature operation, S becomes large, making this problem further serious. In the downsizing age of future computers and so on, when reduction of power is important, the increase of the subthreshold current becomes a substantial problem.
This problem will be further considered taking a memory, which is a typical semiconductor integrated circuit, as an example. The memory generally includes, as shown in FIG. 23, a memory array MA, an X decoder (XDEC) and word driver (WD) for selecting and driving a row line (word line W) for the selection of a memory cell MC within the memory array MA, a sense amplifier (SA) for amplifying the signal on a column line (data line D), a sense amplifier driving circuit (SAD) for driving the sense amplifier, a Y decoder (YDEC) for selecting a column line, and a peripheral circuit (PR) for controlling these circuits. The main parts of these circuits are designed based on the CMOS inverter logic circuit mentioned above.
When the threshold voltage VT of transistors (hereinafter, for simplicity the absolute values of the threshold voltages of the p-channel and n-channel MOS transistors are assumed to be equal to VT) is low, a subthreshold current, that is a current flowing in the source-drain path of the MOS transistors of which the VCS, is substantially 0.
Therefore, the sum of the subthreshold currents becomes particularly great in the circuits having a large number of MOS transistors, such as decoders, drivers or the peripheral circuit section.
For example, in the decoders or drivers, a small number of particular circuits are selected from a i: large number of circuits of the same type by the address signal, and driven. FIG. 24 shows an example of the conventional word driver for DRAM.
If the threshold value VT of the MOS transistors of all CMOS drivers #1-#r is large enough, the subthreshold current, that is a current flowing in the source-drain paths of the MOS transistors of substantially zero VGS, is substantially zero in each of a large number of nonselected circuits. In general, the number of the decoder and driver is increased with the increase of the storage capacity of the memory. However, even though the storage capacity is increased, the total current is not increased unless the subthreshold current flows in the circuits that are not selected in the decoders or drivers.
If the threshold voltage VT is decreased as mentioned above, however, the subthreshold current increases in proportion to the number of nonselected circuits.
In the prior art, when the chip is in the standby mode (nonselected state), almost all the circuits within the chip are turned off so that the power dissipation can be reduced as much as possible. However, it is not possible any more to reduce the power current dissipation even in the standby mode because the subthreshold current flows when the MOS transistors are highly scalled down.
When VT is small, the subthreshold current that is a current flowing in the source-drain paths of the MOS transistors with VGS being substantially zero, causes a trouble not only in the standby mode but also in the operating mode. Generally the current iACT flowing when the chip is in the active mode and the current ISB flowing when the chip is in the standby mode are respectively expressed by
IACT=IOP+IDC, and ISTB=IDC, 
where IOP is the charging and discharging current to and from the load capacitance of the circuits within the chip, and given by
IOP=CTOTxc2x7Vccxc2x7f 
in which Vcc is the operating voltage of the chip, CTOT is the total load capacitance of the circuits within the chip, and f is the operating frequency. In addition, IDC is the subthreshold current given above. The subthreshold current is exponentially increased with the decrease of VT as indicated by the equation (2).
So far, since Vcc is large and VT is also large enough, the condition of
IOP greater than IDC 
can be satisfied. Therefore, the following equations can be given:
IACT=IOP, ISTB=IDC 
In this case, IDC is substantially zero. Thus, for IACT, only the increase of IOP has been considered to cause a problem.
However, since Iis increased with the decrease of Vcc and VT, finally the following condition is satisfied:
IOPxe2x89xa7IDC 
In addition, it is found that if Vcc and VT are decreased, the following condition is given:
IOP less than IDC 
In this case, the expressions of
ACT=IDC, 
ISTB=IDC 
can be given. Therefore, the increase of the subthreshold current IDC also becomes a problem to the current IACT which flows when the chip is operating.
FIG. 25 shows an example of the results predicted for the current dissipation in the DRAM. This prediction is made at a junction temperature of 75xc2x0 C. with typical conditions. From FIG. 25, it will be seen that the IDC Of the 4-G bit DRAM exceeds IOP when its operating voltage is assumed to be 1.2 V.
If we considers the worst conditions, the subthreshold current IDC causes a problem even when the effective channel length, gate oxide film thickness and operating voltage are respectively about 0.25 xcexcm, 6 nm and 2.5 V. Here, the values corresponding to a 256-M bit DRAM are used. In the prior art, when the operating voltage is 3.3 V, the constant current threshold voltage defined as the gate-source voltage of the transistor of which the ratio of the effective channel width to effective channel length is 30 and in which the drain current is 10 nA is one tenth of the operating voltage, or 0.33 V at a substrate-source voltage of 0 volt and a junction temperature of 25xc2x0 C. with typical conditions. At this time, the extrapolated threshold voltage defined as the gate-source voltage when the drain current characteristic of a saturated region is extrapolated for zero current is about 0.2 V higher than the constant current threshold voltage, or about 0.53 V. When the operating voltage is reduced to 2.5 V, the extrapolated threshold voltage is reduced to about 0.4 V in proportion to the operating voltage in order to assure the effective gate voltage. Since the difference between the extrapolated threshold voltage and the constant current threshold voltage is substantially constant, the constant current threshold voltage is about 0.2 V. In addition, the temperature dependency of the threshold voltage must be considered. In general, when the operation of the chip at room temperature is assured, it must be guaranteed at a normal ambient temperature Ta of 0xc2x0 C. through 70xc2x0 C. Moreover, the junction temperature Ti within the chip can be found from the equation of
Tj=Ta+xcex8jaxc2x7Pd 
where Pd is the dissipation power, and xcex8ja is the thermal conductivity of the chip, and thus a higher temperature must be considered. If the source voltage and the active current IACT are 2.5 V and 50 mA, respectively, and if Ta is 75xc2x0 C. including a margin when xcex8ja is 200xc2x0 C./W, the junction temperature Tj is 100xc2x0 C. The constant current threshold voltage at this value of Tj is about 0.1 V when the temperature dependency of the threshold voltage is assumed to be xe2x88x921.6 mV/xc2x0 C. In addition, if we consider the threshold voltage variation due to the process dispersion as 0.1 V, the constant current threshold voltage with 10 nA at the worst condition is about 0.0 V. In this case, if the effective gate length is 0.25 xcexcm, the gate width which is used when defining the constant current threshold voltage is about 7.5 xcexcm. If the total value of gate widths of the MOS transistors within the chip which contributes to IDC is about 4 m, the subthreshold current IDC is found to be 5 mA from the equation (2) when the subthreshold swing S is 100 mV/dec. This value of 5 mnA corresponds to one tenth of IACT as assumed above, and is thus too large to be neglected. Therefore, when the operating voltage is about 2.5 V or below, the subthreshold current in the CMOS logic circuit causes a problem.
We now consider the dissipation power of a CMOS LSI which is demanded for its application. The dissipation power in the LSI used in portable apparatus should be treated as the average dissipation power in the period of time in which it is energized and thus it includes both the standby current and the active current. Particularly in the battery-operated apparatus, both the currents are important because the idle time is determined by the average dissipation power. There are a number of LSIs which keep operating almost within the period of time in which they are energized, such as IC processors, memories and ASICs for high-speed operation. In these LSIs, only the active current is important, and thus the condition of IACT=ISTB may be allowed. In either case, the reduction of IACT is an important subject in all LSIs. In the prior art, since IDC is dominant for ACT in the near future as described above, it becomes important to reduce the leakage (penetrating)., current flowing through the CMOS LSI in the active mode.
Accordingly, it is an object of the invention to provide a semiconductor integrated circuit capable of reducing the dissipation power of the semiconductor integrated circuit including circuits which have enhancement type MOS transistors which operate at an operating voltage of 2.5 V or below and which cause a significant current in the source-drain path when VGS is substantially zero.
It is another object of the invention to reduce the subthreshold current of the MOS transistors included in the word driver, decoder, sense amplifier driving circuit and so on of a memory or a semiconductor integrated circuit in which the memory is incorporated.
In order to achieve the above objects, when some circuits of the semiconductor integrated circuit are operated to change their outputs, the subthreshold current of the MOS transistors in the other circuits which are not changed in their outputs is reduced so that the dissipation power can be decreased.
More specifically, according to this invention, there is provided a semiconductor integrated circuit chip operating at an operating voltage of 2.5 V or below, comprising:
a first terminal at which a first operating potential is applied;
a second terminal at which a second operating potential is applied;
a first circuit block coupled between the first terminal and the second terminal; and
a second circuit block coupled between the first terminal and the second terminal;
wherein the first circuit block permits an active current to flow between the first terminal and the output terminal when the first circuit block responds to an input signal to its input terminal to produce an output signal at its output terminal,
wherein the second circuit block includes a plurality of subcircuit blocks each of which includes a MOS transistor having its source connected to a first node and its gate connected to the input terminal and a load having one end connected to the drain of the MOS transistor and the other end connected to a second node,
wherein the MOS transistor of each of the plurality of subcircuit blocks causes a subthreshold current in its source-drain path when the gate-source voltage is substantially 0,
wherein the plurality of first nodes of the plurality of subcircuit blocks are coupled through a plurality of switching elements to the first terminal, and the plurality of second nodes of the plurality of subcircuit blocks are coupled to the second terminal,
wherein constants of said plurality of switching elements are set so that the leak currents of the plurality of switching elements in their off-state are smaller than the subthreshold current of the MOS transistor of the corresponding one of said plurality of subcircuit blocks, and
wherein the current dissipation in each of the plurality of subcircuit blocks of the second circuit block is limited to a leak current value of the corresponding one of the plurality of switching elements by turning off the plurality of switching elements so that the sum of the current dissipations in the plurality of subcircuit blocks is made smaller than the active current of the first circuit block.
Therefore, even when the semiconductor integrated circuit chip is active, the first circuit block operates within the chip, while the subthreshold current in the non-active second circuit block can be reduced.
In addition, according to this invention, there is provided a semiconductor integrated circuit chip operating at an operating voltage of 2.5 V or below, comprising:
a first terminal at which a first operating potential is applied;
a second terminal at which a second operating potential is applied;
a first circuit block coupled between the first terminal and the second terminal; and
a second circuit block coupled between the first terminal and the second terminal;
wherein the first circuit block permits an active current to flow between the first terminal and the output terminal when the first circuit responds to an input signal to its input terminal to produce an output signal at its output terminal,
wherein the second circuit block includes a plurality of subcircuit blocks each of which includes a MOS transistor having its source connected to a first node and its gate connected to the input terminal and a load having one end connected to the drain of the MOS transistor and the other end connected to a second node,
wherein the MOS transistor of each of the plurality of subcircuit blocks causes a subthreshold current to flow in its source-drain path when the gate-source voltage is substantially 0,
wherein the plurality of first anodes of the plurality of subcircuit blocks are coupled through a plurality of switching elements to the first terminal, and the plurality of second nodes of the plurality of subcircuit blocks are coupled to the second terminal,
wherein constants of said plurality of switching elements are set so that the leak currents of said plurality of switching elements in their off-state are smaller than the subthreshold current of the MOS transistor of the corresponding one of said plurality of subcircuit blocks, and
wherein the current dissipation in each of the plurality of subcircuit blocks of the second circuit block is limited to a leak current value of the corresponding one of the plurality of switching elements by turning off the plurality of switching elements so that the sum of the current dissipations in the plurality of subcircuit blocks is made smaller than the active current of the first circuit block,
wherein each of the plurality of subcircuit blocks of the second circuit block causes an active current to flow between the first terminal and the output terminal of each of the subcircuit blocks when each subcircuit responds to an input signal to its input terminal to produce an output signal at its output,
wherein the first circuit block includes a plurality of subcircuit blocks, each of which includes a MOS transistor having its source connected to the first anode and its gate connected to the input terminal, and a load having its one end connected to the drain of the MOS transistor and the other end connected to the second anode,
wherein the MOS transistor of each of the plurality of subcircuit blocks of the first circuit block causes the subthreshold current to flow in its source-drain path when the gate-source voltage is substantially 0,
wherein the plurality of first anodes of the plurality of subcircuit blocks of the first circuit block are coupled through the plurality of switching elements to the first terminal, and the plurality of second anodes of the plurality of subcircuit blocks of the first circuit block are coupled to the second terminal,
wherein the constants of the plurality of switching elements of the first circuit block are fixed so that the leak currents of the plurality of switching elements of the first circuit block in their off-state are smaller than the threshold current of the MOS transistor of the corresponding one of the plurality of subcircuit blocks of the first circuit block, and
wherein the plurality of subcircuit blocks of the second circuit block are made active by turning on the plurality of switching elements of the second circuit block, and the current dissipation in each of the plurality of subcircuit blocks of the first circuit block is limited to a leak current value of the corresponding one of the plurality of switching elements by turning off the plurality of switching elements of the first circuit block so that the sum of the current dissipations in the plurality of subcircuit blocks is made smaller than that of the active currents of the second circuit block.
Therefore, when the semiconductor integrated circuit chip is active, the first circuit block within the chip is operated, while the subthreshold current in the second non-active circuit block can be reduced. In addition, while the second circuit block is operated within the chip, the subthreshold current in the first non-active circuit block can be reduced.
Moreover, according to this invention, there is provided a semiconductor integrated circuit chip comprising:
a plurality of first circuit blocks;
a plurality of first switching elements;
a first operation potential power line coupled common to the plurality of first switching elements; and
a second switching element coupled between the first operation potential power line and a first operation potential point,
wherein each of a plurality of first nodes of the plurality of first circuit block is coupled to the first operation potential power line through the corresponding one of the plurality of first switching elements,
wherein a plurality of second nodes of the plurality of first circuit blocks are coupled to a second operation potential power line,
wherein each of the plurality of first circuit blocks includes a MOS transistor having its source connected to the corresponding one of the first nodes and its gate connected to an input terminal, and a load having its one end connected to an drain of the MOS transistor and the other end connected to the corresponding one of the second nodes,
wherein the MOS transistor of each of the plurality of first circuit blocks causes a subthreshold current to flow in its source-drain path when the gate-source voltage is substantially 0,
wherein constants of the plurality of first switching elements are set so that the leak current of each of the plurality of first switching elements in its off-state is smaller than the subthreshold current of the MOS transistor of the corresponding one of the plurality of first circuit blocks,
wherein the current dissipation of each of the plurality of first circuit blocks is limited to a leak current value of a corresponding one of the plurality of first switching elements by turning off the plurality of first switching elements, and
wherein a constant of the second switching element is set so that the leak current of the second switching element in its off-state is smaller than the sum of the leak currents of the plurality of first switching elements, and thus the sum of current dissipations in the plurality of first circuit blocks is limited to the leak current value of the second switching element.
Therefore, the current dissipation of each of the plurality of first circuit blocks in the standby mode is limited to the subthreshold current of the first switching elements or below. In addition, the sum of the current dissipations in the plurality of first circuit blocks coupled to the first operation potential line in the standby mode is limited to the subthreshold current of the second switching element or below.
Also, according to this invention, there is provided a semiconductor integrated circuit chip comprising:
a first terminal at which a first operating potential is applied;
a second terminal at which a second operating potential is applied;
a first circuit block coupled between the first terminal and the second terminal; and
a second circuit block coupled between the first terminal and the second terminal;
wherein the first circuit block permits an active current to flow between the first terminal and the output terminal when the first circuit block responds to an input signal to its input terminal to produce an output signal at its output terminal,
wherein the second circuit block includes a plurality of subcircuit blocks each of which includes a MOS transistor having its source connected to a first node and its gate connected to the input terminal and a load having one end connected to the drain of the MOS transistor and the other end connected to a second node,
wherein the MOS transistor of each of the plurality of subcircuit blocks causes a subthreshold current to flow in its source-drain path when the gate-source voltage is substantially 0,
wherein the plurality of first anodes of the plurality of subcircuit blocks are coupled through a plurality of switching elements to the first terminal, and the plurality of second nodes of the plurality of subcircuit blocks are coupled to the second terminal,
wherein constants of said plurality of switching elements are set so that the leak currents of said plurality of switching elements in their off-state are smaller than the subthreshold current of the MOS transistor of the corresponding one of said plurality of subcircuit blocks, and
wherein the current dissipation in each of the plurality of subcircuit blocks of the second circuit block is limited to a leak current value of the corresponding one of the plurality of switching elements by turning off the plurality of switching elements so that the sum of the current dissipations in the plurality of subcircuit blocks is made smaller than the active current of the first circuit block,
wherein each of the plurality of subcircuit blocks of the second circuit block causes an active current to flow between the first terminal and the output terminal of each of the subcircuit blocks when each of the subcircuit blocks of the second circuit block responds to an input signal to its input terminal to produce an output signal at its output,
wherein the first circuit block includes a plurality of subcircuit blocks, each of which includes a MOS transistor having its source connected to the first anode and its gate connected to the input terminal, and a load having its one end connected to the drain of the MOS transistor and the other end connected to the second anode,
wherein the MOS transistor of each of the plurality of subcircuit blocks of the first circuit block causes the subthreshold current to flow in its source-drain path when the gate-source voltage is substantially 0,
wherein the plurality of first anodes of the plurality of subcircuit blocks of the first circuit block are coupled through a plurality of switching elements to the first terminal, and the plurality of second anodes of the plurality of subcircuit blocks of the first circuit block are coupled to the second terminal,
wherein the constants of the plurality of switching elements of the first circuit block are fixed so that the leak currents of the plurality of switching elements of the first circuit block in their off-state are smaller than the threshold current of the MOS transistor of the corresponding one of the plurality of subcircuit blocks of the first circuit block, and
wherein the plurality of subcircuit blocks of the second circuit block are made active by turning on the plurality of switching elements of the second circuit block, and the current dissipation in each of the plurality of subcircuit blocks of the first circuit block is limited to a leak current value of the corresponding one of the plurality of switching elements by turning off the plurality of switching elements of the first circuit block so that the sum of the current dissipations in the plurality of subcircuit blocks is made smaller than that of the active currents of the second circuit block.
Therefore, as described above, the sum of the dissipation currents of the plurality of first circuit blocks coupled to the first operation potential line in the standby mode is limited to the subthreshold current of the second switching element or below, and the sum of the dissipation currents of the plurality of second circuit blocks coupled to the third operation potential line in the standby mode is limited to the subthreshold current of the fourth switching element or below. The total sum of the sum of the dissipation currents in the plurality of first circuit blocks and the sum of the dissipation currents in the plurality of second circuit blocks is limited to the subthreshold current of the fifth switching element or below.
The concept common to the semiconductor integrated circuit chips given in the summary of the invention is to have a plurality of circuit blocks and at least two circuit terminals through which a desired operating voltage is applied to these circuit blocks, and to have current control means provided for the subthreshold currents in the circuit blocks between each of the circuit blocks and at least one of the circuit terminals, so that the leakage current in a certain one of the circuit blocks is controlled by the current control means during a period including part of the time in which at least another one of the circuit blocks logically operates. Thus, when the semiconductor integrated circuit chip itself is in the operating state, during the period in which a certain one of the circuit blocks is operated, the leakage current in another non-operated one of the circuit blocks can be reduced. As a result, it is possible to reduce the total leakage current of the semiconductor integrated circuit chip in the active mode.
Therefore, even if the threshold voltage of the MOS transistor is decreased as it is scaled down, the leakage current flowing in the nonselected circuit can be minimized.